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HV3922 High Voltage PIN Diode Driver
Ordering Information
Package Device HV3922 20 Pin Ceramic DIP HV3922C 28 Pin Ceramic J-Lead HV3922DJ
Features
Processed with HVCMOS(R) technology 5V CMOS logic - low power dissipation DMOS output voltage up to 220V Low power level shifting - 5V to 220V Source current 1.7mA Output fault detection Latched data output
General Description
The HV3922 is a monolithic high-voltage quad-output driver that is designed to be used in conjunction with the Supertex VN2222NC*, a separate N-channel DMOS FET quad array, whose device characterics are briefly described below. Together, these devices per-form a 220V push-pull function that is especially suited for driving PIN diodes in applications such as frequency-hopping radios, microwave communication systems and phased array radar. Used as a microwave or RF switch, the HV3922 has 4 highvoltage P-channel outputs: PD0, PD1, PD2 and PD3. Additional controls are Chip Select (CS) and Output Enable (OE) functions. The HV3922 also has an output fault detection function that protects the outputs from damage by putting them into a high impedance state when a short is detected. The HV3922 provides 4 low-voltage outputs--DRV0, DRV1, DRV2 and DRV3--that drive the gates of the 4 N-channel FETs in the VN2222NC device. See the diagram below for an example of the push-pull output structure that these two devices provide. For detailed electrical characteristics of the VN2222NC, please see the data sheet in Chapter 8. Currently, the HV3922 is available in through-hole and surface-mount ceramic packages that are suitable for military applications, while the VN2222NC is offered in ceramic quad and discrete packages (VN2224N2 and VN2224N3). For commercial product availability, please consult the factory.
Absolute Maximum Ratings
Supply Voltage, VCC Logic Input Voltage Supply Voltage VLL Supply Voltage VPP Max Power Dissipation Junction Temperature Storage Temperature Range Operating Temperature Range Lead Soldering Temperature for 10 Seconds -0.5V to +7.0V -0.3V to VCC + 0.3V -5.0V +230V 0.8W +150 C -65 C to +150 C -55 C to +125 C +300 C
Push-Pull Configuration
VCC CS ENA VHIGH FAULT 220V Push-Pull Output PD0 * * PD3 DRV0 * * DRV3
5V Digital Control 4
HV39
OE D0 - D3
*VN2222NC (1 of 4 FETs)
* VN2222NC is an N-channel DMOS FET quad array recommended for use in conjunction with HV39 outputs to form four 220V push-pull outputs. Each of the four devices has a max RDS(ON) of 1.25, min ID(ON) of 5.0 amps, and BVDSS of 220V.
GND
VLL
VLL
12/13/01
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to 1 workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
HV3922
Electrical Characteristics (over recommended operating conditions unless noted)
DC Characteristics
Symbol ICCQ ILLQ IPPQ IIH IIL VFH VFL VDH VDH VDL VTH(min) VTH(max) VTL(min) VTL(max) Parameter Maximum Quiescent VCC Supply Current Maximum Quiescent VLL Supply Current Maximum Quiescent VPP Supply Current High-level logic current Low-level logic current Minimum high-level logic output voltage (fault detect) Maximum low-level logic output voltage (fault detect) Minimum PD(N) high-level output voltage Minimum DRV(N) high-level output voltage Maximum DRV(N) low-output voltage Minimum fault threshold for PD(N) output high Maximum fault threshold for PD(N) output high Minimum fault threshold for PD(N) output Hi-Z Maximum fault threshold for PD(N) output Hi-Z 0.5 x VPP fault 0.85 x VPP fault V(PDN) = 0V V(PDN) = 25 198 4 -2.3 4.4 0.1 Min Max 1.0 4.0 100 10 10 Units mA mA A A A V V V V V V V V V Conditions VCC = 5.5V All ouputs open VLL= -3.5V DRV(N) high or low VPP = 220V PD(N) high or low H = VCC L = 0V VCC = 4.5V, IOH = 20A VCC = 5.5V, IOL =-20A VPP = 203V, IOH=1.7mA VCC = 4.5V, IOH=100A VLL = -2.5V, IDL = -500A PD(N) = HIGH, OE = VCC PD(N) = HIGH, OE = VCC PD(N) = Hi-Z, OE = VCC PD(N) = Hi-Z, OE = VCC
AC Characteristics (over recommended operating conditions unless noted)
Symbol tWCS tWENA tWOE Parameter Minimum CS pulse to latch data Minimum ENA pulse width to latch data OE pulse width Min 100 100 10 50 Max Units ns ns s Conditions VCC= 4.5V, ENA = 0V VCC= 4.5V, CS = 0V VCC= 4.5V, OE = 0V, VPP = 220V PD(N) LOAD = 20K to GND VPP = 220V, PD(N) LOAD = 20K and 3000pF to GND VCC= 4.5V VCC= 4.5V VCC= 4.5V VCC= 4.5V Not tested, reference only VPP = 220V PD(N) output loaded by 20K ohms & 3000pF to GND
16
50
s
TT TSU1 TSU2 TH CIN TO
Input transition rise and fall times Minimum set-up time DN and CS to ENA Minimum set-up time ENA to OE falling edge Minimum hold time Maximum input capacitance PD(N) transition time from OE low to PD(N) high/low
0 150 150 5
200
ns ns ns ns
10 1 50
pF s
2
HV3922
Recommended Operating Conditions
Symbol VCC VIN VLL VPP IPD(N)H TA CL
Notes: 1.VPP rise time (dv/dt) should be less than 50V/S. 2.Power-up sequence should be the following: A) B) C) D) E) Connect ground; Apply VCC; Apply VLL; Apply VPP; Set all inputs to a known state. Power-down sequence should be the reverse of the above.
Parameter Logic Supply Voltage DC Logic Input Voltage VLL Supply Voltage VPP Supply Voltage High-State Continuous PD(N) Source Current Ambient Operating Temp DRV(N) Load Capacitance
Min 4.5 0 -3.5 200
Max 5.5 VCC -2.5 220 1.7
Units V V V V mA C F
-55 0
+125 0.006
Function Table
Input CS H X L L L L H ENA X H L L L L X OE H H H H H>L H>L H>L Data D(N) X X H L H L X P/F P/F X H H>L X Pass Pass X (At Power Up) X X VIH X P/F Set VDH VDL VFH X H X Fail VTH Level2 Pass Pass Pass Pass P/F P/F Internal Latch Q(N) Previous State Previous State Set Reset Set Reset Previous State Set Reset Previous State Set Reset -- VDH HI-Z HI-Z VDL VDH VDL VFH VFH VFL VDH HI-Z VDL VDH VFH VFH PD(N) Previous State Previous State Previous State Previous State VDH HI-Z Output DRV(N) Previous State Previous State Previous State Previous State VDL VDH Fault VFH VFH VFH VFH VFH VFH
Notes: 1. X indicates "Don't Care" input state (L or H). 2. The output threshold is internally tested for each PD(N) output; the pass condition occurs when OE = H and: A) PD(N) driving high with output > VTH (MAX), or may occurs if PD(N) driving high and output > VTH (MIN) and < VTL (MAX). OR B) PD(N) driving Low with output < VTH (MIN), or may occur if PD(N) driving low and output < VTH (MAX) and < VTL (MIN). The fail condition occurs when OE = H and conditions for "pass" are not satisfied. 3. Fault output = VFL indicates a fault has been detected in at least one of the PD(N) output loads when OE = H. All other outputs shall function normally when a fault condition has been detected for one of the outputs. The Fault output shall remain in the low state, regardless of the state of the output which initiated the fault status, until the next falling edge of OE. Whenever OE = L, the Fault output is forced to VFH, and the fault latch is reset. If the fault condition persists, the fault response repeats each time the OE input is set to H. 4. H>L indicates falling edge (H to L). 5. HI-Z indicates no current is sourced to output PD(N). 6. P/F indicates "Pass" or "Fail" fault threshold conditions.
3
HV3922
Functional Block Diagram
VPP VCC VLL GND Drive Circuit V PP
OE
Gate Control Circuit
Voltage Sense
PD0
DO
Q Latch Set
FF CLK Set
Q
DRV0 Fault 0
ENA CS D1 Q Latch Set Q PD1 DRV1
FF CLK Set
Drive Circuit 1
D2
Q Latch Set
FF CLK Set
Q
Drive Circuit 2
PD2 DRV2
D3
Q Latch Set
FF CLK Set
Q
Drive Circuit 3
PD3 DRV3
Fault Power-Up Circuit
Timing Diagram
DATA LOW and CS 10% tWCS 90% DATA HIGH tSU1 TH 90% ENA 10% tWENA TT OE 90% 10% tWOE tSU2 PD(N) tOH 90% 10% 10% TT 10% 90% 10%
DRV(N)
4
HV3922
Pin Configurations
20 Pin, 300 Mil Wide Package Pin Function 1 D1 2 D2 3 D3 4 VLL 5 GND 6 DRV3 7 DRV2 8 PD3 9 PD2 10 PD1 Pin 11 12 13 14 15 16 17 18 19 20 Function PD0 DRV1 DRV0 VPP VCC ENA OE CS Fault D0
Package Outline
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
20 Pin, 300 Mil Wide DIP HV3922C
28 Pin, J-Lead Package Pin Function 1 D1 2 D2 3 D3 4 N/C 5 VLL 6 GND 7 N/C 8 DRV3 9 DRV2 10 N/C 11 PD3 12 N/C 13 PD2 14 N/C
Pin 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Function PD1 PD0 N/C DRV1 DRV0 N/C VPP N/C VCC ENA OE CS Fault D0
25 26
27
24
23
22
21
20
19 18 17 16 15 14 13 12
28 1 2 3 4 5 6 7 8 9 10 11
28 Pin J-Lead Package HV3922DJ
20 Pin, 300 Mil Wide Package Pin Function 1 S 2 S 3 S 4 G1 5 G2 6 G3 7 G4 8 S 9 S 10 S
1
20 19 18 17 16 15 14 13 12 11
Pin 11 12 13 14 15 16 17 18 19 20
Function S S N/C D4 D3 D2 D1 N/C S S
2 3 4 5 6 7 8 9 10
20 Pin, 300 Mil Wide DIP VN2222NC
12/13/010
(c)2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
5
1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 * FAX: (408) 222-4895 www.supertex.com

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